The IEEE 1149.1 Joint Test Action Group (JTAG) standard defines a serial test methodology that uses serial test circuitry in integrated circuit chips to access test data registers and to control and observe signals between devices on a printed circuit board. As shown in FIG. 1, a four-wire interface consisting of a Test Clock (TCK) pin, a Test Mode Select (TMS) pin, a Test Data Input (TDI) pin, and a Test Data Output (TDO) pin are used to control a Test Access Port (TAP) control state machine 102 in every 1149.1-compliant device. In response to JTAG instructions shifted into the device through the TCK, TMS, and TDI pins, the TAP controller can select between multiple data registers inside the device to shift data into through the TDI pin or from which to bring data out to the TDO pin.
This test methodology allows 1149.1-compliant devices to be serially chained together on a board or across multiple boards. TCK and TMS signals are connected to the TCK and TMS pins of all devices in this chain, while the TDI and TDO pins of each device in this chain are connected in series. Software can access JTAG test data registers on any device in the chain, and can also check or set the state of any pin on any device in this chain by serially shifting in data on the TDI pin of a first device under control of TCK and TMS, and monitoring the serial data output TDO pin of a last device. The standard was originally developed to simplify board interconnect testing by enabling easy access to any pin on a device, especially on the higher-pin count and finer-pitch devices. Connections can be tested by driving known values on one or more pins of one or more JTAG devices, and then confirming that expected values are detected on one or more pins of one or more JTAG devices.
FIG. 2 shows the state machine implemented by the TAP controller 102 of a 1149.1-compliant device. Test Access port controller 102 is controlled by the test clock TCK and TEST mode select TMS inputs. These two inputs determine whether an instruction register (IR) scan or a data register (DR) scan is performed. TAP controller 102 is driven by the TCK signal, which responds to the states of the TMS signal as shown in FIG. 2.
FIG. 3 shows a simplified circuit diagram of a 1149.1-compliant circuit controlled by TAP controller 102. Data on the TDI pin are routed by de-multiplexer 303 to one of several destinations under control of TAP controller 102. These include the boundary scan structure 108, instruction register 103, a bypass register 104, and a user data register 105 illustrated in FIG. 1. The structure of FIG. 3 shows additional registers 301, 302, and 305 provided in some Xilinx, Inc. FPGA devices for configuring and identifying the FPGA. Multiplexer 304, also under control of TAP controller 102 shifts data out to the TDO pin.
FIG. 4 shows circuitry for implementing boundary scan logic in a typical input/output block (IOB) of a Xilinx Inc. chip. The illustration of FIG. 4 shows a single pin 441 and the input/output buffer (IOB) and boundary scan test data register circuitry 400 associated with that pin. The IOBI (IOB input) line is an input into the IOB, IOBO (IOB output) is the output from the IOB, and IOBT (IOB tristate control) is the control signal generated to control the IOB buffer. In the chip there are many such pins with associated IOBs and boundary scan circuits. This boundary scan chain is selected by the TAP controller to be connected between TDI and TDO when a JTAG test instruction that uses the aforementioned scan chain is loaded.
Three flip flops 401, 402, and 403 may be serially connected by multiplexers 411, 412, and 413 into a shift register. These flip flops may also store and provide input and output signals to and from the interior of the chip during JTAG test operations. These flip flops form part of the boundary scan chain and are connected serially by placing a logic 1 onto the Shift/Capture line. These flip flops capture the input and output states of the IOB when a logic 0 is placed on the Shift/Capture line. Update latches 404, 405, 406 accompany flip flops 401, 402, 403 and are used to hold input test data stable during shifting of data through the boundary scan chain. A buffer 421 drives output signals from line 462 onto pin 441 as controlled by a tristate signal on line 464.
The operation of circuitry 400 is controlled by TCK and control signals from the TAP: Shift/Capture, Update, and EXTEST. When shift/capture line 451 is at logic 1, the boundary scan shift register is enabled and data can be shifted into or out of the boundary scan registers. In a typical operation, data bits are applied to the TDI pin and shifted through the boundary scan chain under control of the TAP controller. Proper operation of the shift register can be observed by pulsing high the Update signal to capture the boundary scan data from flip flops 401 to 403 into latches 404 to 406, then asserting high the EXTEST signal to apply the test data in latch 405 to pin 441. For example if a stream of data applied to the TDI pin includes a logic 1 that arrives at flip flop 403 followed by a selected value (1 or 0) that arrives at flip flop 402, a high Update pulse moves this logic 1 and the selected value to latches 406 and 405. A logic 1 EXTEST value causes multiplexers 416 and 415 to apply the values in latches 406 and 405 to buffer 421. The logic 1 in latch 406 turns on buffer 421 so that the value in latch 405 is applied to pin 441 for external observation. The value shifted into register 401 and updated into latch 404 will be sent to the interior of the chip as signal IOBI through multiplexer 414.
When the EXTEST line is held at logic 0, normal I/O operation is selected. Multiplexer 414 forwards the signal on pin 441 to the interior of the chip as signal IO3I. Also, an input signal on pin 441 is forwarded by multiplexer 411 to flip flop 401 for capture on the next TCK and UPDATE. The IOBO value on line 461 will go to output buffer 421, and will be driven onto pin 441 if the buffer 421 is turned on by the IOBT value on line 463.
To avoid letting line 453 and pin 441 float when no active signal is on line 453, one of weak transistors 431 and 432 is turned on, to pull line 453 high or low (as controlled by the pull-up/pull-down block).
Prior Uses of Boundary Scan Circuits
In addition to board testing, some integrated circuit manufacturers use this four-wire interface to send programming instructions and data to configure programmable logic devices in-system.
One way to configure programmable logic devices is to incorporate programming registers and control logic into a JTAG 1149.1-compliant programmable chip. Such a chip can be configured by serially loading programming address and/or data into one or more of the programming registers through the TAP interface, and then loading a program instruction through the same interface to instruct the chip to perform the programming operation. A controller in the JTAG 1149.1-compliant chip will generate the necessary control signal sequences to configure its programmable cells with the loaded data.
If a programmable chip does not have JTAG circuitry, then programming data and instructions can be sent to it by connecting the programming data and control lines of the non-JTAG device to a JTAG device.
FIG. 5 shows a JTAG-compliant chip 100 with boundary scan being used to program a flash memory chip 200. IO pins of the JTAG chip 100 are connected to the address, data, and control lines of the flash chip 200. Programming address, data, and control signals for the flash chip 200 are serially shifted into the boundary scan register chain of the JTAG chip 100 until the required values are loaded into the boundary scan registers controlling the appropriate IO pin of the JTAG chip 100. The address, data, and control signals in the boundary scan registers are then driven out to the IO pins of the JTAG chip 100 using a standard EXTEST JTAG instruction. To generate a data programming sequence for a flash memory from a JTAG chip using this method requires multiple boundary scan register load and EXTEST operations.
For example: flash memory chip 200 requires a pulse on its write enable pin WE while its data and address pins are driven with values specifying the data value to write and the memory location to write to. The boundary scan register of the JTAG chip must be serially loaded with values to drive the data pins to the required data value, the address to the specified location, and the write enable line to the inactive state. An EXTEST instruction is then loaded into the JTAG chip 100 to drive these address, data, and (inactive) write enable values to the IO pins connected to the flash chip 200. The boundary scan register is then serially loaded with values to drive the same address and data values, but now the boundary scan cells for the write enable pin must be loaded with the appropriate bits to drive the write enable signal to an active state. Another EXTEST instruction drives these values to the IO pins. During these two operations, the address and data lines will retain the same values, but the write enable pin will now be switched from inactive to active. For a third time, the boundary scan register chain is serially loaded with bits to hold the same address and data values, and the write enable boundary scan cells are loaded with values to set the write enable pin back to the inactive state. Another EXTEST instruction will drive the same address and data values onto the IO pins, and the write enable pin will now be driven back to the inactive state to complete the write operation for this memory location. The time required to perform a write operation will depend on the length of the boundary scan register chain. JTAG chips with more pins will have longer boundary scan chains.
A read operation is performed similarly: the read address is serially loaded and then driven to the IO pins of the JTAG device using EXTEST. A standard JTAG SAMPLE instruction is executed on the JTAG chip to sample the flash chip data lines connected to the IO pins of the JTAG chip by loading them into the input boundary scan cells. These sampled data values are then shifted out through TDO to a JTAG test system for processing.
It is desirable to continue using a JTAG chip for configuring a non-JTAG chip, but to increase the speed with which data can be shifted into position to be transferred to or from the other non-JTAG chip 200 (such as a flash memory chip).